Compound semiconductor monolithic ICs, such as GaAs MMICs (monolithic microwave integrated circuits), are devices made of a compound semiconductor material that has electron transport properties employed most effectively for realizing high speed FET elements mounted in the ICs. Thus, compound semiconductor MMICs are intended for integrated circuits used in satellites, mobile telephones, and milliwave integrated circuits or the like. Further, in recent years, compound semiconductor MMICs have been in high demand because of the development of mobile radios.
Since MMICs are applicable to high power amplifiers mobile radios or satellites, in addition to improvement of high frequency properties of transistors, they must endure heat generated by the transistor itself and prolonged use under severe circumstances. Therefore, extremely high reliability is generally demanded of the MMICs. Especially in gate, source, and drain electrodes which determine reliability of an FET, a Schottky, or an ohmic junction with the compound semiconductor is employed. Therefore, in order to improve reliability, a solid phase reaction between a metal and a semiconductor should be suppressed satisfactorily.
Generally, a refractory metal is employed for a gate electrode to improve a heat resistance. For example, a field effect transistor with a self-aligned refractory metal electrode has a planar element structure. The planar field effect transistor is unstable in operation and has a low breakdown voltage, and excess current flows in the vicinity of a GaAs surface when employed in a high power amplifier. Therefore, the planar field effect transistor is exclusively employed as a switching element or a low noise amplifier. However, both high power and low price are demanded of a transistor used in a portable telephone, so that such a transistor has the planar FET structure.
In order to obtain superior high power properties that the planar field effect transistor cannot achieve, an element structure in which a recess or a well is formed in a compound semiconductor substrate and in the center of which the refractory metal gate is disposed, is effective. In this element structure, no excess current flows in the vicinity of the substrate surface, so that a transistor with this element structure is employed as a circuit element of a high power amplifier.
However, an expensive substrate is required to realize this structure. The structure is not suitable for a transistor especially used in a portable telephone requiring a low price. Accordingly, in many cases, the structure applies to a high power amplifier in equipment for a satellite in which, generally, a low price is not demanded.
It is impossible to realize a high power device with improved high power properties usable in a microwave band and also in a milliwave band using GaAs series semiconductor elements. At present, companies and research institutes are keenly competing with each other. Of the possible semiconductor elements that can realize such a high frequency and high power device, an InP series HEMT that uses InGaAs, having an electron mobility twice as high as that of GaAs, is the most promising. An InP series HEMT is supposed to be realized shortly.
However, in InGaAs and AlInAs constituting an InP HEMT, a noticeable solid phase reaction between a metal material and the InP is observed and reliability is poor, so that a refractory metal must be used for the source and drain electrodes as well as the gate electrode. Accordingly, it is difficult to fabricate an HEMT with source and drain electrodes made of such a refractory metal, and such an HEMT has yet to be realized.
Further, low cost and high performance are demanded of other circuit elements as well as transistors. Therefore, its capacitors and filters must also be miniaturized.
A capacitor according to the present invention referred to as an MIM (metal-insulator-metal) has a dielectric thin film sandwiched between metal regions. The capacitor is used for an impedance matching circuit, a filter for RF blocking (high-pass filter) and DC blocking in the MMIC.
A filter according to the present invention referred to as a film bulk acoustic wave resonator has the same structure as the MIM capacitor and differs from the capacitor in that a piezoelectric film is employed between metal regions. The filter is located in a rear stage of a mixer in a circuit and prevents propagation of radio waves other than at a predetermined frequency. There is a need for reducing power loss in the filter to improve efficiency. In particular, since the film bulk acoustic wave resonator is used at a frequency of 2 GHz or more, it is an essential element in a portable telephone.
Under the circumstances, in order to realize a cheap high power amplifier, the inventors of the present invention have developed a semiconductor device wherein the refractory metal gate electrode is disposed self-alignedly in the center of the bottom portion of the recess and a self-aligning process, such as an ion implantation process, is employed for formation of source and drain regions (see Japanese Patent Application Nos. Hei. 6-154717 and Hei. 7-66094). A description of that semiconductor device and a method of fabricating it follows.
FIG. 29(e) is a cross-sectional view illustrating a semiconductor device disclosed in Japanese Patent Application No. Hei. 6-154717. In the figure, reference numeral 201 designates a self-aligned FET (hereinafter referred to as an SAGFET) having a conventional recess gate structure. The gate electrode 16a is formed self-alignedly in a recess 1a of a substrate surface. The recess 1a is formed in the surface of the compound semiconductor substrate 1 of the FET 201. In the center of the bottom portion of the recess 1a, a refractory metal gate electrode 16a made of a refractory metal is disposed as a Schottky electrode. Immediately under the gate electrode of the semiconductor substrate 1, an n diffusion region 2 is formed. At both sides of the n diffusion region 2 at the bottom of the recess 1a, low-concentration diffusion regions (n' diffusion regions) 3a, 3b are formed. Under the n diffusion region 2 and the n' diffusion regions 3a, 3b, of the semiconductor substrate 1, a p diffusion region 5 is formed.
At both sides of the recess 1a of the semiconductor substrate 1, n.sup.+ diffusion regions 4a, 4b are formed as source and drain regions. An entire surface on the substrate is covered by an insulating film 17. On the n.sup.+ diffusion regions 4a, 4b, of the insulating film 17, openings 17a, 17b are formed spaced apart from an edge of the recess 1a by a prescribed distance. In the openings of the insulating film, source and drain electrodes 8a, 8b are disposed as ohmic electrodes.
As described above, the refractory metal gate electrode 16a is located in the center of the recess 1a and has a planar surface. A distance between the gate electrode 16a and the n.sup.+ source diffusion region 4a is equal to a distance between the gate electrode 16a and the drain diffusion region 4b. The n diffusion region 2 is present only immediately under the refractory metal gate electrode 16a and serves as a channel region. The n.sup.+ diffusion regions 3a, 3b are present only at the bottom of the recess 1a except for the n diffusion region 2. The n.sup.+ diffusion regions 4a, 4b are present outside the recess 1a, and have a thickness larger than those of the n diffusion region 2, and the n' diffusion regions 3a, 3b. Bottoms of the n.sup.+ diffusion regions 4a, 4b are coplanar with a boundary between the n diffusion region 2 and the n' diffusion regions 3a, 3b, and the p diffusion region 5.
A description will be given of a fabrication method. FIGS. 27(a)-27(f), FIGS. 28(a)-(28e) and FIGS. 29(a)-29(e) illustrate a fabrication method of the SAGFET 201. As illustrated in FIG. 27(a), SiO.sub.2 is deposited over the compound semiconductor substrate 1 to a thickness of about 3000 .ANG. to form an insulating film 41. Thereafter, a resist 42 having a prescribed pattern opening 42a is formed.
As illustrated in FIG. 27(b), the insulating film 41 is selectively etched using the resist 42 as a mask to form an opening 41a. In this case, RIE (Reactive Ion Etching) is employed, which is easy of etching perpendicular to the substrate surface.
As illustrated in FIG. 27(c), after removal of the resist 42, dry etching of the compound semiconductor substrate 1 by Cl.sub.2 is performed using the insulating film 41 as a mask, to form the recess 1a having about 500 .ANG. thickness. Alternatively, the recess 1a may be formed by wet etching using an aqueous solution of tartaric acid and hydrogen peroxide mixed in a ratio of 50:1. As described above, after removal of the resist 42, the recess 1a is formed. Alternatively, the recess 1a may be formed before removal of the resist 42.
As illustrated in FIG. 27(d), an ion implantation using the insulating film 41 as a mask is performed to form the n diffusion region 2 at the bottom of the recess 1a and the p diffusion region 5 under the same. At this time, although ions are also implanted into the insulating film 41 used as a mask, the concentration is about 10.sup.17 cm.sup.-3, so that the composition of the insulating film 41 is hardly changed. In this ion implantation, Si ions are employed for formation of the n diffusion region 2 and Mg ions are employed for formation of the p diffusion region 5. The Si ions are implanted at an accelerating energy of 60 KeV and a dose of about 7.times.10.sup.12 cm.sup.-2. The Mg ions are implanted at an accelerating energy of 300 KeV and a dose of about 5.times.10.sup.12 cm.sup.-2.
Since implanted depth of the ions is about 1000 .ANG. in case of the Mg ions implanted at a high accelerating energy, the insulating film 41 comprising SiO.sub.2 film 3000 .ANG. thick sufficiently serves as a mask for the ion implantation.
As illustrated in FIG. 27(e), a refractory metal thin film 16 is deposited over the entire surface. At this time, it is important that no discontinuity of the refractory metal thin film 16 occurs in the upper portion of the opening of the recess 1a. As a material of the refractory metal thin film 16, WSi, WSiN, WN, TiW, or the like is employed. The thickness of the refractory metal thin film 16 and width of the coverage of the refractory metal thin film 16 on the step part at both sides of the recess 1a (dimension in gate length direction) determines widths of the n' diffusion region 3a, 3b and the gate length.
For example, when the width of the coverage is 0.25 .mu.m and the opening width of the recess is 1.0 .mu.m, the gate length becomes 0.5 .mu.m. As a method of depositing the refractory metal thin film 16, sputter deposition or blanket CVD is employed. The sputter deposition provides an arched-top gate electrode. The blanket CVD provides a flat-top gate electrode.
As illustrated in FIG. 27(f), a second resist 45 is formed on the refractory metal thin film 16. The second resist 45 is applied to a thickness of 1 .mu.m sufficient to make the recess 16b of the refractory metal thin film 16 corresponding to the recess 1a flat. A material resistant to RIE is used for the second resist 45.
Thereafter, as illustrated in FIG. 28(a), the second resist 45 is etched using an etching technique that provides a high uniformity across a wafer, such as O.sub.2 ashing. The etching is stopped when the refractory metal thin film 16 is exposed. Since the ratio of the second resist 45 filling the recess 16b of the refractory metal thin film 16 to the entire surface of the wafer is small, light emission from CO is suddenly reduced when the refractory metal thin film 16 is exposed. Therefore, if the light emission from CO is monitored during the etching, the etching is stopped upon detection of sudden reduction of the light emission from CO when the refractory metal thin film 16 is exposed, leaving the resist 45a with high controllability.
As illustrated in FIG. 28(b), using the resist 45a as a mask, the refractory metal thin film 16 is etched. An etching technique that hardly damages or etches the n diffusion region 2, such as plasma etching or ECR etching, is employed. As an etching gas, SF.sub.6 or CF.sub.4 +O.sub.2 is employed. The etching is stopped after over-etching for about several tens of seconds (3000 .ANG. in terms of film thickness) from the point (end point) when the insulating film 41 is exposed. The end point of the etching is easily detected by monitoring light emission from F radicals or light emission from SiF.
As illustrated in FIG. 28(c), after removal of the second resist 45a, Si ions are implanted to form n' diffusion regions 3a, 3b. The Si ions are implanted at an accelerating energy of 60 KeV as in the ion implantation for the n diffusion region 2 so that the bottom of the n' diffusion region 3 is coplanar with the bottom of the n diffusion region 2. The dose depends on the desired breakdown voltage and transconductance of elements.
As illustrated in FIG. 28(d), a third resist 47 is formed. The thickness of the third resist 47 is about 1 .mu.m, sufficient to bury the recess opening and the refractory metal gate electrode 16a.
As illustrated in FIG. 28(e), the third resist 47 is etched by O.sub.2 ashing, and the etching is stopped when the insulating film 41 is exposed. The principle and the method for detecting the end point of the etching are identical to those already described for the etching of the second resist 45. In order to avoid unwanted mixing of a resist masking a region of the substrate where the FET is not formed with the resist 47a left in the recess 1a in a subsequent ion implantation process for formation of the n.sup.+ diffusion regions 4a, 4b, the resist 47a must be reformed by deep UV curing.
Thereafter, as illustrated in FIG. 29(a), the insulating film 41 is removed. The removal of the insulating film 41 is performed with buffered hydrofluoric acid (HF:NH.sub.4 F=30:1). It is important that the refractory metal gate electrode 16a, the third resist 47a and the compound semiconductor substrate 1 are not damaged and no residue is left.
As illustrated in FIG. 29(b), using the refractory metal gate 16a and the resist 47a as masks, Si ions are implanted to form n.sup.+ diffusion regions 4a, 4b. A region on the substrate where the FET is not formed is masked with a resist (not shown). The energy of the ion implantation is set at 60-70 KeV so that the resist 47a can mask the Si ions and, preferably, the bottoms of the n.sup.+ diffusion regions 4a, 4b are coplanar with the bottoms of the n diffusion region 2 and the n' diffusion regions 3a, 3b. The dose is about 5.times.10.sup.13 cm.sup.-2.
As illustrated in FIG. 29(c), after removal of the third resist 47a, ion-implanted regions are activated by annealing. The annealing is performed at about 800.degree. C. for about 30 minutes in an ambient including As.
As illustrated in FIG. 29(d), an insulating 17 for passivation is deposited over the entire surface. Preferably, the insulating film 17 has a stress of 1.times.10.sup.9 dyn/cm.sup.2 or less between the substrate and the same to suppress the short channel effect. For example, an SiON film formed by plasma CVD is employed as the insulating film.
Finally, a resist (not shown) having openings corresponding to regions where source and drain electrodes are to be formed is formed on the insulating film 17. Using the resist as a mask, the insulating film 17 is etched to form openings 17a, 17b therein. Thereafter, ohmic metals, i.e., source and drain electrodes 8a, 8b are formed in the openings of the insulating film using the evaporation and lift-off technique, followed by sintering, whereby an FET 201 is completed.
The source and drain electrodes 8a, 8b have a structure in which an AuGe based alloy is laminated on an Ni region to reduce contact resistance.
As illustrated in FIG. 29(e), a top surface of the refractory metal gate 16a of the completed FET is smooth and flat.
In this FET 201, since the refractory metal gate electrode 16a is disposed in the center of the bottom portion of the recess, a high power transistor is obtained. Further, since the source and drain regions 4a, 4b are formed self-alignedly with respect to the gate electrode 16a, by ion implantation, inexpensive elements are obtained because fabrication process is simplified. However, channel current tends to be adversely affected by a trap produced at an interface between the n' diffusion regions 3a, 3b beside the gate electrode and the insulating film 17. In addition, it is difficult to control widths (dimension in gate length direction) of the n' diffusion regions 3a, 3b.
Further, the p diffusion region 5, the n diffusion region 2, and the n' diffusion regions 3a, 3b, which are different in concentration, are provided in common. Therefore, optimization of the p diffusion region 5, i.e., optimization of positioning boundaries between the n diffusion region 2 and the p diffusion region 5, and the n' diffusion regions 3a, 3b and the p diffusion region 5 cannot be achieved. As a result, improvement of high frequency properties does not coexist with suppression of the short channel effect.
The inventors have invented an improved FET that has overcome the problems described above. A description of the improved FET follows (see Japanese Patent application No. Hei 7-66094).
FIG. 33(d) is a cross-sectional view illustrating a semiconductor device described in Japanese Patent application No. 7-66094). In the figure, numeral 202 designates the improved FET having a conventional recess gate structure. In a surface of a compound semiconductor substrate 1, a recess 1a is formed and in the center of the recess 1a, a recess 1b is formed. In the recess 1b in the center of the bottom portion of the recess 1a, a refractory metal gate electrode 26a made of a refractory metal material and having a T-shaped cross section is disposed as a Schottky electrode. In the lower portion of the gate electrode of the semiconductor substrate 1, an n diffusion region 2 is formed as a channel region. At both sides of the recess 1b at the bottom of the recess 1a, n' diffusion regions 3a, 3b are formed as low-concentration source and drain regions.
As in the FET 201, at both sides of the recess 1a of the semiconductor substrate 1, n.sup.+ diffusion regions 4a, 4b are formed as high-concentration source and drain regions. Surfaces of the diffusion regions 4a, 4b, an inner surface of the recess 1a and a surface of the gate electrode 26a are covered by an insulating film 27 for passivation.
On the n.sup.+ diffusion regions 4a, 4b in the insulating film 27, spaced apart from an edge of the recess 1a by a prescribed distance, openings 27a, 27b are formed. In the openings of the insulating film, source and drain electrodes 8a, 8b are disposed as ohmic electrodes.
A distance between a source-side bottom of the refractory gate electrode 26a and the n.sup.+ source diffusion region 4a is equal to a distance between a drain-side bottom of the gate electrode 26a and the n.sup.+ drain diffusion region 4b. The n diffusion region 2 serving as a channel region is present only immediately under the refractory metal gate electrode 26a. The n' diffusion regions 3a, 3b are present only at the bottom of the recess 1a except for the n diffusion region 2. The n.sup.+ diffusion regions 4a, 4b are present outside the recess. The thickness of the n.sup.+ diffusion regions 4a, 4b is larger than those of the n diffusion region 2 and the n' diffusion regions 3a, 3b.
In the improved FET 202 having such a structure, the refractory metal gate electrode 26a is located in the center of the recess 1b which has one more step in the recess 1a, so that channel current is hardly affected by a depletion region present at an interface between the n' diffusion region 3a, 3b and the insulating film 27. Since a carrier trap is produced at the interface between the n' diffusion regions 3a, 3b and the insulating film 27, the fact that the channel current is hardly affected by the depletion region means that the charge and discharge time of carriers in the trap does not determine the response speed of the FET. That is, transconductance gm and an operation speed of the FET are not reduced.
A description will be given of a fabrication method of the improved FET 202. FIGS. 30(a)-30(b), FIGS. 31(a)-31(d), FIGS. 32(a)-32(d), and FIGS. 33(a)-33(d) are views illustrating a fabrication method of the SAGFET 202. As illustrated in FIG. 30(a), the insulating film 41 is deposited to a thickness of about 4000 .ANG. on the compound semiconductor substrate 1 to form a resist 42 having a prescribed pattern opening 42a thereon.
As illustrated in FIG. 30(b), using the resist 42 as a mask, the insulating film 41 is etched to form the opening 41a therein. An SiO.sub.2 film is employed as the insulating film 41. The insulating film 41 is etched by RIE which easily etches perpendicular to the substrate surface.
As illustrated in FIG. 30(c), after removal of the resist film 42, using the insulating film 41 as a mask, the compound semiconductor substrate 1 is etched to form the recess 1a about 500 .ANG. deep in the substrate 1. At this time, the recess 1a may be formed before removal of the resist 42. For the recess etching in the compound semiconductor substrate 1, wet etching using an aqueous solution of tartaric acid and hydrogen peroxide mixed in a ratio of 50:1 or dry etching using Cl.sub.2 is employed. FIG. 30(c) illustrates a recess 1a, which is formed by the etching perpendicular to a substrate surface using the dry etching.
As illustrated in FIG. 30(d), the insulating film 43 is deposited over the entire surface. At this time, it is important that no discontinuity of the insulating film 43 occurs in the opening of the recess 1a. SiN or the like is used as a material of the insulating film 43. The width of the coverage of the insulating film 43 on the step part in the recess opening end, and the thickness of the insulating film 43 determine the widths of the n' diffusion regions 3a, 3b and the gate length. For example, if the width of the coverage is 0.25 .mu.m and the width of the recess opening (dimension in gate length direction) is 1.0 .mu.m, the gate length becomes 0.5 .mu.m. As a method of depositing the insulating film 43, plasma CVD or blanket CVD is employed. The former provides an arched-top recess of the insulating film 43. The latter provides a flat-top recess.
As illustrated in FIG. 30(e), a second resist 45 is deposited over the entire surface. At this time, application of the resist 45 is performed so that the film thickness thereof can make the recess 43b of the insulating film 43 sufficiently even. For example, the second resist 45 is resistant to RIE, and is applied to about 1 .mu.m thickness.
Thereafter, as illustrated in FIG. 31(a), the second resist 45 is etched using an etching technique that provides a high uniformity across a wafer, such as O.sub.2 ashing. The etching is stopped when the insulating film 43 is exposed. Since the ratio of the resist 45a filling the recess 43b of the insulating film 43 to the entire surface of the wafer is small, if light emission from CO is monitored during the etching, sudden reduction of the light emission from CO is detected when the insulating film 43 is exposed. Therefore, the etching is stopped by detecting reduction of the light emission from CO, whereby the resist 45a is left in the recess 43b of the insulating film 43 with high controllability.
As illustrated in FIG. 31(b), the insulating film 43 is etched using the second resist 45 as a mask. Preferably, an etching technique that hardly damages or etches a GaAs surface, such as plasma etching or ECR etching, is employed. The etching is stopped when the insulating film 43 is exposed. As a result, a dummy gate 43a is formed of the insulating film 43. The end point of the etching can be easily detected by monitoring the light emission from F radical or from SiF.
As illustrated in FIG. 31(c), after removal of the second resist 45a, Si ions are implanted to form n' diffusion regions 3a, 3b. The energy of ion implantation is set at 60 KeV so that the thickness of the n' diffusion regions 3a, 3b becomes about 1000 .ANG.. The dose depends on the breakdown voltage and transconductance of the element.
As illustrated in FIG. 31(d), a third resist 47 is applied over the entire surface. The thickness of the resist 47 is about 1 .mu.m, enough to bury the recess opening and the dummy gate 43a formed of the insulating film 43.
Then, as illustrated in FIG. 32(a), the third resist 47 is etched by O.sub.2 ashing, and the etching is stopped when the insulating film 41 is exposed. The principle and the method for detecting the end point of the etching are identical to those already described for the etching of the second resist 45. In order to avoid unwanted mixing of a resist masking a region on the substrate where the FET is not fabricated with the third resist 47a buried at both sides of the dummy gate 43a formed of the insulating film, in a subsequent ion implantation process for making n.sup.+ diffusion regions 4a, 4b, the resist 47a must be reformed by deep UV curing.
As illustrated in FIG. 32(b), the dummy gate 43a is removed. As an etching technique, plasma etching using an etching gas such as SF.sub.6, NF.sub.3 is employed. At this time, when using an SiO film as the insulating film 41 and an SiN film as the insulating film 43, the etching rates of the resist 47 and the SiO film are 100 .ANG./min. and the etching rate of the SiN film is 200 .ANG./min. so that only the dummy gate 43a comprising the SiN film is selectively etched. In addition, the substrate where the dummy gate is removed is etched.
As in formation of the recess 1a in the compound semiconductor substrate 1, for the etching in this case, wet etching using an aqueous solution of tartaric acid and hydrogen peroxide mixed in a ratio of 50:1 or dry etching using Cl.sub.2 is employed. However, in order to keep the refractory metal gate electrode 26a from contacting the n' diffusion regions 3a, 3b, the former is more preferable. When using the dry etching using Cl.sub.2, as long as it is an isotropic etching, the refractory metal gate electrode 26a is kept from contacting the n' diffusion regions, 3a, 3b. Keeping the refractory metal gate electrode 26a from contacting the n' diffusion regions 3a, 3b is effective in increasing the gate breakdown voltage of the FET.
As illustrated in FIG. 32(c), Si ions are implanted to form the n diffusion region 2. The energy of ion implantation is set at 60 KeV so that the thickness of the n diffusion regions becomes 1000 .ANG.. The dose depends on the desired pinch-off voltage.
As illustrated in FIG. 32(d), the refractory metal thin film 26 is deposited over the entire surface. In this case, as a material of the refractory metal thin film 26, WSi, WSiN, WN, Ti, or the like is employed, and the refractory metal thin film 26 has some thickness so that no discontinuity occurs in the recess.
Thereafter, as illustrated in FIG. 33(a), a resist 48 which has a pattern corresponding to a gate pattern is formed. Using the resist 48 as a mask, the refractory metal thin film 26 is etched. As an etching technique, RIE is employed, which is easily etched perpendicular to the substrate surface, and CF.sub.4 +O.sub.2 is employed as an etching gas. The etching is stopped after over etching about several tens of seconds (about 3000 .ANG. in terms of film thickness), from the end point when the insulating film 41 is exposed. At this time, the end point can be detected with ease by monitoring light emission from SiF.
The insulating film 41 is letched with buffered hydrofluoric acid (HF:NH.sub.4 F=30:1). At this time, it is important that the refractory metal gate electrode 26a, the third resist 47a and the compound semiconductor substrate 1 are not damaged and no residue is left. In order to avoid unwanted mixing of the resist 48 with the resist 47 buried at both sides of the dummy gate and the resist masking a region on the substrate where the FET is not fabricated, in a subsequent ion implantation process for formation of the n.sup.+ diffusion region, the resist 48 must be reformed by deep UV curing.
As illustrated in FIG. 33(b), using the refractory metal gate electrode 26a, the resist 47a and the resist 48 as masks, Si ions are implanted to form the n.sup.+ diffusion regions 4a, 4b. A region on the substrate where the FET is not present is masked with a resist (not shown). The energy of the Si ion implantation is about 150 KeV, and it is desired that the bottoms of the n.sup.+ diffusion regions 4a, 4b be coplanar with those of the n diffusion region 2 and the n' diffusion regions 3a, 3b. The dose is about 5.times.10.sup.13 cm.sup.-2.
As illustrated in FIG. 33(c), after removal of the third resist 47a and the resist 48, the ion-implanted regions are activated by annealing. The annealing of the substrate is performed at about 800.degree. C. for about 30 minutes in an ambient including As, by heating.
As illustrated in FIG. 33(d), the insulating film 27 for passivation is deposited. The insulating film 27 must have a stress of 1.times.10.sup.9 dyn/cm.sup.2 or less between the substrate and the same to suppress the short channel effect due to a stress applied to the substrate. For example, SiON film or the like formed by plasma CVD is employed as the insulating film 27.
Finally, the insulating film 27 is etched using a resist film which has openings corresponding to regions where the source and drain electrodes are to be formed, as a mask, to form openings 27a, 27b of the insulating film. Thereafter, ohmic metals, i.e., source and drain electrodes 8a, 8b are formed using the evaporation and lift-off technique, followed by sintering, whereby an FET 202 is completed. The source and drain electrodes 8a, 8b have a structure in which an AuGe based alloy is laminated on an Ni region to reduce a contact resistance.
The FET 202 fabricated using the above-described method has the following advantages. First, since the dummy gate 43a is used, the thickness of the gate electrode 26a and the widths of the n' diffusion regions 3a, 3b are determined independently. In the method illustrated in FIGS. 27-29, in order to increase the widths of the n' diffusion regions 3a, 3b, the refractory metal thin film 16 must be thickened, so that the gate electrode 16a of the FET is made thicker. This means that the effect on the FET properties due to a stress applied to the substrate by the gate electrode 16a (gate stress) or process shape of the gate electrode is varied in accordance with the variations of the widths of the n' diffusion regions 3a, 3b, leading to unstable device properties.
In the FET 202 fabricated using the method illustrated in FIGS. 30-33, since the widths of the n' diffusion regions 3a, 3b are set by the dummy gate 43a, the film thickness of the gate electrode 26a and widths of the n' diffusion regions 3a, 3b are determined independently. This means that the effect on FET properties due to the gate stress and process shape is not varied depending on the widths of the n' diffusion regions 3a, 3b, whereby stable transistor properties are not adversely affected.
Secondly, since the implantation energy for formation of the n.sup.+ diffusion regions 4a, 4b is increased, the bottoms of the n.sup.+ diffusion regions 4a, 4b are coplanar with the bottoms of the n diffusion region 2 and n' diffusion regions 3a, 3b. In the method illustrated in FIGS. 27-29, the energy of the ion implantation is set at 60-70 KeV for masking of the implanted ions by the resist 47, so that the bottoms of the n.sup.+ diffusion regions 4a, 4b are not coplanar with the bottoms of the n diffusion region 2 and the n' diffusion regions 3a, 3b. This causes an increase in a resistance between the gate and the channel and between the gate and the drain and a reduction of transconductance gm.
On the other hand, in the FET 202 fabricated using the method illustrated in FIGS. 30-33, the resist 47a, the resist 48 and the refractory metal thin film 26a can prevent implanted ions and the bottoms of the n.sup.+ diffusion regions 4a, 4b are coplanar with the bottoms of the n diffusion regions 2 and the n' diffusion regions 3a, 3b at a high energy of 150 KeV. In this case, the resistances between the gate and the source, and the gate and drain can be reduced to the limit, so that the maximum transconductance gm can be obtained. The gate electrode is buried in the recess of the substrate surface as described above. This means that there is no current in excess in the substrate surface.
In this method, the ion implantation process for formation of the n diffusion region 2 as a channel region, the n' source and drain diffusion regions 3a, 3b is performed independently. The p type diffusion region can be optimized, since in the ion implantation process for formation of the n diffusion region ions are implanted for formation of the p diffusion region under the n diffusion region, and in the ion implantation process for formation of the n' diffusion regions 3a, 3b, ions are implanted for formation of the p' diffusion region 51 under the n' diffusion region 3a, 3b.
In Japanese Patent Application No. Hei. 7-66094, structures of recess type SAGFETs and a method of fabricating the SAGFETS are described, wherein the p diffusion region is present only under the n diffusion region 2 and the n' diffusion regions 3a, 3b, or the p' diffusion region is present only under the n' diffusion regions 3a, 3b, which will not be described herein.
A description is given of an InP series HEMT which can realize a high power device in the milliwave band as well as in the microwave band with improved high power properties.
The InP series HEMT has a structure described in Loi D. Nguyen et al., IEEE Transactions on Electron Devices, volume 39, 1992, pages 2007-2014, and is fabricated as a low noise amplifier in the milliwave band because of high operation frequency thereof.
However, the gate electrode has a Ti/Pt/Au structure (Pt and Au regions laminated on a Ti region) and the source and drain electrodes have a AuGe/Ni/Au structure (Ni and Au regions laminated on an AuGe region). Therefore, a noticeable solid phase reaction between these electrodes and InGaAs, AlInAs, i.e., a compound semiconductor constituting the InP series HEMT, is observed and reliability of the device is poor. As a result, refractory metals must be used for the source and drain electrodes as well as the gate electrode.
One of the attempts is a trial product of an InP-HEMT introduced in a reference (H. Sasaki et al., IPRM, 1995, pages 745-748), wherein a refractory metal WSi is used only for the source and drain electrodes for higher reliability.
However, in a structure described in the reference, Ti is used as the gate electrode material and a fluorine-containing gas is used for processing WSi for the material of the source and drain electrodes. Therefore, a noticeable solid phase reaction between the gate electrode and AlInAs is observed and fluorine diffuses into the AlInAs region, so that improved reliability of the high power device cannot be achieved.
Accordingly, a refractory metal material must be used for the gate electrode and a fluorine-containing gas must not be used in a formation process of the gate electrode. However, nothing is suitable as the process gas except for fluorine-containing gases, so that it is difficult to meet such a demand, which is not realized.
A description will be given of a structure and characteristics of an MIM capacitor for use in an existing compound semiconductor MMIC. A dielectric used in the MIM capacitor comprises an SiN film or SiON film formed by plasma CVD. This is because oxidation of the compound semiconductor, such as GaAs or InP cannot form an insulating film of good quality, so that a silicon thermal oxidation (SiO.sub.2) film with a reliability of a silicon device cannot be employed as the insulating film.
As conventional, in the fabrication method of the compound MMIC capacitor, an MIM structure is employed. The MIM structure comprises a metal region formed using the evaporation and lift-off technique, an SiN film or an SiON film deposited thereon by plasma CVD and a metal region formed thereon using the evaporation and lift-off technique. In order to increase the capacitance of the capacitor, the thickness of the dielectric film must be reduced, or a dielectric constant of a dielectric material must be increased.
In the former method, for example, if the thickness of the SiN film as the dielectric film is reduced from 1000 .ANG. to 500 .ANG., twice the capacitance is obtained. However, in this case, the insulating breakdown voltage is reduced from 100 V to 50 V, resulting in the compound MMIC capacitor with poor reliability. On the other hand, in the latter method, for example, when using a ferroelectric material having a dielectric constant of about 100, such as SrTiO.sub.3 as a dielectric material, several times the capacitance is obtained without reducing the breakdown voltage. The film of the dielectric region must be thickened for ensuring the breakdown voltage, so that an MIM capacitor with 100 times capacitance is not obtained using a ferroelectric material having a dielectric constant about 100 times as high as a normal dielectric material.
However, since processing of ferroelectric material has several problems, application to the compound MMIC is limited. First, considerable stress is produced between the ferroelectric material and the metal film, and the film is thickened to ensure the insulating breakdown voltage, so that the dielectric region tends to peel. Secondly, wet etching in processing provides poor precision, a large pattern edge, and a side-etched structure, so that a large margin is required to prevent etching the dielectric region itself constituting the MIM capacitor. To increase a process precision, dry etching using HBr may be employed which has a high corrosivity and is difficult to handle.
Therefore, there is a need for an MIM capacitor which is easy to fabricate and provides high precision.
The film bulk acoustic wave resonator also has a structure which is similar to that of the MIM capacitor wherein the dielectric region is replaced by a piezoelectric region. As in the MIM capacitor, thickening the piezoelectric region for improved properties causes the same to peel, and a large margin of the etching pattern must be left when using wet etching in a fabrication process. To increase process precision, dry etching may be employed which uses a highly-corrosive etching gas and is difficult to handle.
A brief description will be given of problems of the prior art FET, HEMT, MIM capacitor, and a film bulk acoustic wave resonator. In the prior art FET 202 illustrated in FIG. 33(d), reduction of the effect of traps produced at the interface between the n' diffusion regions 3a, 3b and the insulating film 27, control of widths of the n' diffusion regions 3a, 3b and optimization of the p diffusion region 5 are realized, so that high frequency properties are improved and the short channel effect is suppressed. However, the gate length of the refractory metal gate electrode 26a formed by etching in the recess 1a, i.e., the dummy gate 43a, is determined by the time of over etching in the recess 1a and variation of the process, so that it is difficult to control the gate length.
Though the prior art InP series HEMT has sufficiently high frequency properties in the operation in the milliwave band, sufficient reliability of high power devices is not obtained.
In the prior art MIM capacitor and film bulk acoustic wave resonator, when using a thick ferroelectric region to increase breakdown voltage and capacitance, the ferroelectric region tends to peel, leading to a fragile device structure. Since an etching with high precision with respect to the ferroelectric material requires a highly-corrosive etching gas, desired processing is not compatible with precision.